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d a t a sh eet product speci?cation supersedes data of december 1990 file under integrated circuits, ic06 1998 jan 23 integrated circuits 74hc/hct40105 4-bit x 16-word fifo register for a complete data sheet, please also download: the ic06 74hc/hct/hcu/hcmos logic family specifications
1998 jan 23 2 philips semiconductors product speci?cation 4-bit x 16-word fifo register 74hc/hct40105 features independent asynchronous inputs and outputs expandable in either direction reset capability status indicators on inputs and outputs 3-state outputs output capability: standard i cc category: msi general description the 74hc/hct40105 are high-speed si-gate cmos devices and are pin compatible with the 40105 of the 4000b series. they are specified in compliance with jedec standard no. 7a. the 74hc/hct40105 are first-in/first-out (fifo) elastic storage registers that can store sixteen 4-bit words. the 40105 is capable of handling input and output data at different shifting rates. this feature makes it particularly useful as a buffer between asynchronous systems. each word position in the register is clocked by a control flip-flop, which stores a marker bit. a 1 signifies that the positions data is filled and a 0 denotes a vacancy in that position. the control flip-flop detects the state of the preceding flip-flop and communicates its own status to the succeeding flip-flop. when a control flip-flop is in the 0 state and sees a 1 in the preceding flip-flop, it generates a clock pulse that transfers data from the preceding four data latches into its own four data latches and resets the preceding flip-flop to 0. the first and last control flip-flops have buffered outputs. since all empty locations bubble automatically to the input end, and all valid data ripples through to the output end, the status of the first control flip-flop (data-in ready output - dir) indicates if the fifo is full, and the status of the last flip-flop (data-out ready output - dor) indicates if the fifo contains data. as the earliest data is removed from the bottom of the data stack (output end), all data entered later will automatically ripple toward the output. quick reference data gnd = 0 v; t amb = 25 c; t r = t f = 6 ns notes 1. c pd is used to determine the dynamic power dissipation (p d in m w): p d = c pd v cc 2 f i +? (c l v cc 2 f o ) where: f i = input frequency in mhz. f o = output frequency in mhz. ? (c l v cc 2 f o ) = sum of outputs c l = output load capacitance in pf v cc = supply voltage in v 2. for hc the condition is v i = gnd to v cc for hct the condition is v i = gnd to v cc - 1.5 symbol parameter conditions typ. unit hc hct t phl / t plh propagation delay c l = 15 pf; v cc =5 v mr to dir, dor 16 15 ns so to q n 37 35 ns t phl propagation delay si to dir 16 18 ns so to dor 17 18 ns f max maximum clock frequency 33 31 mhz c i input capacitance 3.5 3.5 pf c pd power dissipation capacitance per package notes 1 and 2 134 145 pf
1998 jan 23 3 philips semiconductors product speci?cation 4-bit x 16-word fifo register 74hc/hct40105 ordering information pin description type number package name description version 74hc(t)40105n dip16 plastic dual in-line package; 16 leads (300 mil); long body sot38-1 74hc(t)40105d so16 plastic small outline package; 16 leads; body width 3.9 mm sot109-1 74hc(t)40105db ssop16 plastic shrink small outline package; 16 leads; body width 5.3 mm sot338-1 74hc(t)40105pw tssop16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 pin no. symbol name and function 1 oe output enable input (active low) 2 dir data-in ready output 3 si shift-in input (low-to-high, edge-triggered) 4, 5, 6, 7 d 0 to d 3 parallel data inputs 8 gnd ground (0 v) 9 mr asynchronous master reset input (active high) 13, 12, 11, 10 q 0 to q 3 3-state data outputs 14 dor data-out ready output 15 so shift-out input (high-to-low, edge-triggered) 16 v cc positive supply voltage fig.1 pin configuration. fig.2 logic symbol. fig.3 iec logic symbol.
1998 jan 23 4 philips semiconductors product speci?cation 4-bit x 16-word fifo register 74hc/hct40105 input and outputs data inputs (d 0 to d 3 ) as there is no weighting of the inputs, any input can be assigned as the msb. the size of the fifo memory can be reduced from the 4 16 configuration, i.e. 3 16, down to 1 16, by tying unused data input pins to v cc or gnd. data outputs (q 0 to q 3 ) as there is no weighting of the outputs, any output can be assigned as the msb. the size of the fifo memory can be reduced from the 4 16 configuration as described for data inputs. in a reduced format, the unused data outputs pins must be left open circuit. master-reset (mr) when mr is high, the control functions within the fifo are cleared, and date content is declared invalid. the data-in ready (dir) flag is set high and the data-out-ready (dor) flag is set low. the output stage remains in the state of the last word that was shifted out, or in the random state existing at power-up. status ?ag outputs (dir, dor) indication of the status of the fifo is given by two status flags, data-in-ready (dir) and data-out-ready (dor): dir = high indicates the input stage is empty and ready to accept valid data; dir = low indicates that the fifo is full or that a previous shift-in operation is not complete (busy); dor = high assures valid data is present at the outputs q 0 to q 3 (does not indicate that new data is awaiting transfer into the output stage); dor = low indicates the output stage is busy or there is no valid data. shift-in control (si) data is loaded into the input stage on a low-to-high transition of si. it also triggers an automatic data transfer process (ripple through). if si is held high during reset, data will be loaded at the falling edge of the mr signal. shift-out control ( so) a high-to-low transition of so causes the dor flags to go low. a high-to-low transition of so causes upstream data to move into the output stage, and empty locations to move towards the input stage (bubble-up). output enable ( oe) the outputs q 0 to q 3 are enabled when oe = low. when oe = high the outputs are in the high impedance off-state. functional description data input following power-up, the master-reset (mr) input is pulsed high to clear the fifo memory (see fig.8). the data-in-ready flag (dir = high) indicates that the fifo input stage is empty and ready to receive data. when dir is valid (high), data present at d 0 to d 3 can be shifted-in using the si control input. with si = high, data is shifted into the input stage and a busy indication is given by dir going low. the data remains at the first location in the fifo until dir is set to high and data moves through the fifo to the output stage, or to the last empty location. if the fifo is not full after the si pulse, dir again becomes valid (high) to indicate that space is available in the fifo. the dir flag remains low if the fifo is full (see fig.6). the si use must be made low in order to complete the shift-in process. with the fifo full, si can be held high until a shift-out ( so) pulse occurs. then, following a shift-out of data, an empty location appears at the fifo input and dir goes high to allow the next data to be shifted-in. this remains at the first fifo location until si goes low (see fig.7). data transfer after data has been transferred from the input stage of the fifo following si = low, data moves through the fifo asynchronously and is stacked at the output end of the register. empty locations appear at the input end of the fifo as data moves through the device. data output the data-out-ready flag (dor = high) indicates that there is valid data at the output (q 0 to q 3 ). the initial master-reset at power-on (mr = high) sets dor to low (see fig.8). after mr = low, data shifted into the fifo moves through to the output stage causing dor to go high. as the dor flag goes high, data can be shifted-out using the so = high, data in the output stage is shifted out and a busy indication is given by dor going low. when so is made low, data moves through the fifo to fill the output stage and an empty location appears at the input stage. when the output stage is filled dor goes high, but if the last of the valid data has been shifted-out leaving the fifo empty the dor flag remains low (see fig.9). with the fifo empty, the last word that was shifted-out is latched at the output q 0 to q 3 . with the fifo empty, the so input can be held high until the si control input is used. following an si pulse,
1998 jan 23 5 philips semiconductors product speci?cation 4-bit x 16-word fifo register 74hc/hct40105 data moves through the fifo to the output stage, resulting in the dor flag pulsing high and a shift-out of data occurring. the so control must be made low before additional data can be shifted-out (see fig.10). high-speed burst mode if it is assumed that the shift-in/shift-out pulses are not applied until the respective status flags are valid, it follows that the shift-in/shift-out rates are determined by the status flags. however, without the status flags a high-speed burst mode can be implemented. in this mode, the burst-in/ burst-out rates are determined by the pulse widths of the shift-in/shift-out inputs and burst rates of 35 mhz can be obtained. shift pulses can be applied without regard to the status flags but shift-in pulses that would overflow the storage capacity of the fifo are not allowed (see figs 11 and 12). expanded format with the addition of a logic gate, the fifo is easily expanded to increase word length (see fig.17). the basic operation and timing are identical to a single fifo, with the exception of an additional gate delay on the flag outputs. if during application, the following occurs: si is held high when the fifo is empty, some additional logic is required to produce a composite dir pulse (see figs 7 and 18). due to the part-to-part spread of the ripple through time, the si signals of fifo a and fifo b will not always coincide and the and-gate will not produce a composite flag signal. the solution is given in fig.18. the 40105 is easily cascaded to increase the word capacity and no external components are needed. in the cascaded configuration, all necessary communications and timing are performed by the fifos. the intercommunication speed is determined by the minimum flag pulse widths and the flag delays. the data rate of cascaded devices is typically 25 mhz. word-capacity can be expanded to and beyond 32-words 4-bits (see fig.19).
1998 jan 23 6 philips semiconductors product speci?cation 4-bit x 16-word fifo register 74hc/hct40105 fig.4 functional diagram. fig.5 logic diagram. (see control flip-flops) (1) low on s input of ff1, and ff5 will set q output to high independent of state on r input. (2) low on r input of ff2, ff3 and ff4 will set q output to low independent of state on s input.
1998 jan 23 7 philips semiconductors product speci?cation 4-bit x 16-word fifo register 74hc/hct40105 dc characteristics for 74hc for the dc characteristics see 74hc/hct/hcu/hcmos logic family specifications . output capability: standard i cc category: msi ac characteristics for 74hc gnd = 0 v; t f = t f = 6 ns; c l = 50 pf symbol parameter t amb ( c) unit test conditions 74hc v cc (v) waveforms + 25 - 40 to + 85 - 40 to + 125 min. typ. max. min. max. min. max. t phl / t plh propagation delay mr to dir, dor 52 175 220 265 ns 2.0 fig.8 19 35 44 53 4.5 15 30 37 45 6.0 t phl propagation delay si to dir 52 210 265 315 ns 2.0 fig.6 19 42 53 63 4.5 15 36 45 54 6.0 t phl propagation delay so to dor 55 210 265 315 ns 2.0 fig.9 20 42 53 63 4.5 16 36 45 54 6.0 t phl / t plh propagation delay so to q n 116 400 500 600 ns 2.0 fig.14 42 80 100 120 4.5 34 68 85 102 6.0 t plh propagation delay/ ripple through delay si to dor 564 2000 2500 3000 ns 2.0 fig.10 205 400 500 600 4.5 165 340 425 510 6.0 t plh propagation delay/ bubble-up delay so to dir 701 2500 3125 3750 ns 2.0 fig.7 255 500 625 750 4.5 204 425 532 638 6.0 t pzh / t pzl 3-state output enable time oe to q n 41 150 190 225 ns 2.0 fig.16 15 30 38 45 4.5 12 26 33 38 6.0 t phz / t plz 3-state output disable time oe to q n 41 140 175 210 ns 2.0 fig.16 15 28 35 42 4.5 12 24 30 36 6.0 t thl / t tlh output transition time 19 75 95 110 ns 2.0 fig.14 7 15 19 22 4.5 6 13 16 19 6.0 t w si pulse width high or low 80 19 100 120 ns 2.0 fig.6 16 7 20 24 4.5 14 6 17 20 6.0
1998 jan 23 8 philips semiconductors product speci?cation 4-bit x 16-word fifo register 74hc/hct40105 t w so pulse width high or low 120 39 150 180 ns 2.0 fig.9 24 14 30 36 4.5 20 11 26 31 6.0 t w dir pulse width high 12 58 180 10 225 10 270 ns 2.0 fig.7 6 21 36 5 45 5 54 4.5 5 17 31 4 38 4 46 6.0 t w dor pulse width low 12 55 170 10 215 10 255 ns 2.0 fig.9 6 20 34 5 43 5 51 4.5 5 16 29 4 37 4 43 6.0 t w mr pulse width high 80 22 100 120 ns 2.0 fig.8 16 8 20 24 4.5 14 6 17 20 6.0 t rem removal time mr to si 50 14 65 75 ns 2.0 fig.15 10 5 13 15 4.5 9 4 11 13 6.0 t su set-up time d n to si - 5 - 39 - 5 - 5 ns 2.0 fig.13 - 5 - 14 - 5 - 5 4.5 - 5 - 11 - 5 - 5 6.0 t h hold time d n to si 125 44 155 190 ns 2.0 fig.13 25 16 31 38 4.5 21 13 26 32 6.0 f max maximum pulse frequency si, so using ?ags or burst mode 3.6 10 2.8 2.4 mhz 2.0 fig.6, 9, 11 and 12 18 30 14 12 4.5 21 36 16 14 6.0 f max maximum pulse frequency si, so cascaded 3.6 10 2.8 2.4 mhz 2.0 figs 6 and 9 18 30 14 12 4.5 21 36 16 14 6.0 symbol parameter t amb ( c) unit test conditions 74hc v cc (v) waveforms + 25 - 40 to + 85 - 40 to + 125 min. typ. max. min. max. min. max.
1998 jan 23 9 philips semiconductors product speci?cation 4-bit x 16-word fifo register 74hc/hct40105 dc characteristics for 74hct for the dc characteristics see 74hc/hct/hcu/hcmos logic family specifications . output capability: standard i cc category: msi note to hct types the value of additional quiescent supply current ( d i cc ) for a unit load of 1 is given in the family specifications. to determine d i cc per input, multiply this value by the unit load coefficient shown in the table below. ac characteristics for 74hct gnd = 0 v; t f = t f = 6 ns; c l = 50 pf input unit load coefficient oe 0.75 si 0.40 d n 0.30 mr 1.50 so 0.40 symbol parameter t amb ( c) unit test conditions 74hct v cc (v) waveforms + 25 - 40 to + 85 - 40 to + 125 min. typ. max. min. max. min. max. t phl / t plh propagation delay mr to dir, dor 18 35 44 53 ns 4.5 fig.8 t phl propagation delay si to dir 21 42 53 63 ns 4.5 fig.6 t phl propagation delay so to dor 20 42 53 63 ns 4.5 fig.9 t phl / t plh propagation delay so to q n 40 80 100 120 ns 4.5 fig.14 t plh propagation delay/ ripple through delay si to dor 188 400 500 600 ns 4.5 fig.10 t plh propagation delay/ bubble-up delay so to dir 244 500 625 750 ns 4.5 fig.7 t pzh / t pzl 3-state output enable time oe to q n 18 35 44 53 ns 4.5 fig.16 t phz / t plz 3-state output disable time oe to q n 15 30 38 45 ns 4.5 fig.16 t thl / t tlh output transition time 7 15 19 22 ns 4.5 fig.14
1998 jan 23 10 philips semiconductors product speci?cation 4-bit x 16-word fifo register 74hc/hct40105 t w si pulse width high or low 16 6 20 24 ns 4.5 fig.6 t w so pulse width high or low 16 7 20 24 ns 4.5 fig.9 t w dir pulse width high or low 6 20 34 5 43 5 51 ns 4.5 fig.7 t w dor pulse width high or low 6 19 34 5 43 5 51 ns 4.5 fig.9 t w mr pulse width high 16 7 20 24 ns 4.5 fig.8 t rem removal time mr to si 15 7 19 22 ns 4.5 fig.15 t su set-up time d n to si - 5 - 14 - 4 - 4 ns 4.5 fig.13 t h hold time d n to si 27 16 34 41 ns 4.5 fig.13 f max maximum pulse frequency si, so using ?ags or burst mode 28 12 10 mhz 4.5 fig.6, 9, 11 and 12 f max maximum pulse frequency si, so cascaded 28 12 10 mhz 4.5 figs 6 and 9 symbol parameter t amb ( c) unit test conditions 74hct v cc (v) waveforms + 25 - 40 to + 85 - 40 to + 125 min. typ. max. min. max. min. max.
1998 jan 23 11 philips semiconductors product speci?cation 4-bit x 16-word fifo register 74hc/hct40105 ac waveforms shifting in sequence fifo empty to fifo full fig.6 waveforms showing the si input to dir output propagation delay. the si pulse width and si maximum pulse frequency. (1) hc : v m = 50%; v i = gnd to v cc . hct : v m = 1.3 v; v i = gnd to 3 v. notes to fig.6 1. dir initially high; fifo is prepared for valid data. 2. si set high; data loaded into input stage. 3. dir drops low, input stage busy. 4. dir goes high, status flag indicates fifo prepared for additional data; data from first location ripple through. 5. si set low; necessary to complete shift-in process. 6. repeat process to load 2nd word through to 16th word into fifo. 7. dir remains low: with attempt to shift into full fifo, no data transfer occurs. with fifo full; si held high in anticipation of empty location fig.7 waveforms showing bubble-up delay, so input to dir output and dir output pulse width. (1) hc : v m = 50%; v i = gnd to v cc . hct : v m = 1.3 v; v i = gnd to 3 v. notes to fig.7 1. fifo is initially, shift-in is held high. 2. so pulse; data in the output stage is unloaded, bubble-up process of empty locations begins. 3. dir high; when empty location reached input stage, flag indicates fifo is prepared for data input. 4. dir returns to low; fifo is full again. 5. si brought low; necessary to complete whidt-in process, dir remains low, because fifo is full.
1998 jan 23 12 philips semiconductors product speci?cation 4-bit x 16-word fifo register 74hc/hct40105 master reset applied with fifo full fig.8 waveforms showing the mr input to dir, dor output propagation delays and the mr pulse width. (1) hc : v m = 50%; v i = gnd to v cc . hct : v m = 1.3 v; v i = gnd to 3 v. notes to fig.8 1. dir low, output ready high; assume fifo is full. 2. mr pulse high; clears fifo. 3. dir goes high; flag indicates input prepared for valid data. 4. dor drops low; flag indicates fifo empty. shifting out sequence; fifo full to fifo empty fig.9 waveforms showing the so input to dir output propagation delay. the so pulse width and so maximum pulse frequency. (1) hc : v m = 50%; v i = gnd to v cc . hct : v m = 1.3 v; v i = gnd to 3 v. notes to fig.9 1. dor high; no data transfer in progress, valid data is present at output stage. 2. so set high. 3. so is set low; data in the input stage is unloaded, and new data replaces it as empty location bubbles-up to input stage. 4. dor drops low; output stage busy. 5. dor goes high; transfer process completed, valid data present at output after the specified propagation delay. 6. repeat process to unloaded the 3rd through to the 16th word from fifo. 7. dor remains low; fifo is empty.
1998 jan 23 13 philips semiconductors product speci?cation 4-bit x 16-word fifo register 74hc/hct40105 with fifo empty; so is held high in anticipation fig.10 waveforms showing ripple through delay si input to dor output and propagation delay from the dor pulse to the q n output. (1) hc : v m = 50%; v i = gnd to v cc . hct : v m = 1.3 v; v i = gnd to 3 v. agewidth mba337 t phl / t plh v m (1) si input so input dor output q output n v m (1) v m (1) 2 1 t plh ripple through delay 4 5 6 t phl 3 notes to fig.10 1. fifo is initially empty, so is held high. 2. si pulse; loads data into fifo and initiates ripple through process. 3. dor flag signals the arrival of valid data at the output stage. 4. output transition; data arrives at output stage after the specified propagation delay between the rising edge of the dor pulse to the q n output. 5. so set low; necessary to complete shift-out process. dor remains low, because fifo is empty. 6. dor goes low; fifo is empty again. shift-in operation; high-speed burst mode fig.11 waveforms showing si minimum pulse width and si maximum pulse frequency, in high-speed shift-in burst mode. (1) hc : v m = 50%; v i = gnd to v cc . hct : v m = 1.3 v; v i = gnd to 3 v. note to fig.11 in the high-speed mode, the burst-in rate is determined by the minimum shift-in high and shift-in low specifications. the dir status flag is a dont care condition, and a shift-in pulse can be applied regardless of the flag. a si pulse which would overflow the storage capacity of the fifo is ignored.
1998 jan 23 14 philips semiconductors product speci?cation 4-bit x 16-word fifo register 74hc/hct40105 shift-out operation; high-speed burst mode fig.12 waveforms showing so minimum pulse width and maximum pulse frequency, in high-speed shift-out burst mode. in the high-speed mode, the burst-out rate is determined by the minimum shift-out high and shift-out low specifications. the dor flag is a dont care condition and a so pulse can be applied without regard to the flag. (1) hc : v m = 50%; v i = gnd to v cc . hct : v m = 1.3 v; v i = gnd to 3 v. fig.13 waveforms showing hold and set up times for d n input to si input. the shaded areas indicate when the input is permitted to change for predictable output performance. (1) hc : v m = 50%; v i = gnd to v cc . hct : v m = 1.3 v; v i = gnd to 3 v. fig.14 waveforms showing so input to q n output propagation delays and output transition time. (1) hc : v m = 50%; v i = gnd to v cc . hct : v m = 1.3 v; v i = gnd to 3 v.
1998 jan 23 15 philips semiconductors product speci?cation 4-bit x 16-word fifo register 74hc/hct40105 fig.15 waveforms showing the mr input to si input removal time. (1) hc : v m = 50%; v i = gnd to v cc . hct : v m = 1.3 v; v i = gnd to 3 v. handbook, halfpage mba332 v m (1) v m (1) t rem mr input si input fig.16 waveforms showing the 3-state enable and disable times for input oe. (1) hc : v m = 50%; v i = gnd to v cc . hct : v m = 1.3 v; v i = gnd to 3 v.
1998 jan 23 16 philips semiconductors product speci?cation 4-bit x 16-word fifo register 74hc/hct40105 application information fig.17 expanded fifo for increased word length; 16 words 8 bits. the pc74hc/hct40105 is easily expanded to increase word length. composite dir and dor flags are formed with the addition of an and gate. the basic operation and timing are identical to a single fifo, with the exception of an added gate delay on the flags. fig.18 expanded fifo for increased word length. this circuit is only required if the si input is constantly held high, when the fifo is empty and the automatic shift-in cycles are started (see fig.7).
1998 jan 23 17 philips semiconductors product speci?cation 4-bit x 16-word fifo register 74hc/hct40105 expanded format fig.19 shows two cascaded fifos providing a capacity of 32 words 4 bits fig.20 shows the signals on the nodes of both fifos after the application of a si pulse, when both fifos are initially empty. after a rippled through delay, date arrives at the output of fifo a . due to so a being high, a dor pulse is generated. the requirements of si b and d nb are satisfied by the dor a pulse width and the timing between the rising edge of dor a and q na . after a second ripple through delay, data arrives at the output of fifo b . fig.21 shows the signals on the nodes of both fifos after the application of a so r pulse, when both fifos are initially full. after a bubble-up delay a dir r pulse is generated, which acts as a so a pulse for fifo a . one word is transferred from the output of fifo a to the input of fifo b . the requirements of the so a pulse for fifo a is satisfied by the pulse width of dor b . after a second bubble-up delay an empty space arrives at d na , at which time dir a goes high. fig.22 shows the waveforms at all external nodes of both fifos during a complete shift-in and shift-out sequence. fig.19 cascading for increased word capacity; 32 words 4 bits. the pc7hc/hct40105 is easily cascaded to increase word capacity without any external circuitry. in cascaded format, all necessa ry communications are handled by the fifos. figs 17 and 19 demonstrate the intercommunication timing between fifo a and fifo b . fig.22 gives an overview of pulse and timing of two cascaded fifos, when shifted full and shifted empty again.
1998 jan 23 18 philips semiconductors product speci?cation 4-bit x 16-word fifo register 74hc/hct40105 fig.20 fifo to fifo communication; input timing under empty condition. (1) hc : v m = 50%; v i = gnd to v cc . hct : v m = 1.3 v; v i = gnd to 3 v. notes to fig.20 1. fifo a and fifo b initially empty, so a held high in anticipation of data. 2. load one word into fifo a ; si pulse applied, results in dir pulse. 3. data out a /data in b transition; valid data arrives at fifo a output stage after a specified delay of the dor flag, meeting data input set-up requirements of fifo b . 4. dor a and si b pulse high; (ripple through delay after si a low) data is unloaded from fifo a as a result of the data output ready pulse, data is shifted into fifo b . 5. dir b and so a go low; flag indicates input stage of fifo b is busy, shift-out of fifo a is complete. 6. dir b and so a go high automatically; the input stage of fifo b is again able to receive data, so is held high in anticipation of additional data. 7. dor b goes high; (ripple through delay after si b low) valid data is present one propagation delay later at the fifo b output stage. (1) hc : v m = 50%; v i = gnd to v cc . hct : v m = 1.3 v; v i = gnd to 3 v. fig.21 fifo to fifo communication; output timing under full condition. notes to fig.21 1. fifo a and fifo b initially empty, si b held high in anticipation of shifting in new data as empty location bubbles-up. 2. unload one word into fifo b ; so pulse applied, results in dor pulse. 3. dir b and so a pulse high; (bubble-up delay after so b low) data is loaded into fifo b as a result of the dir pulse, data is shifted out of fifo a . 4. dor a and si b go low; flag indicates the output stage of fifo a is busy, shift-in to fifo r is complete. 5. dor a and si b go high; flag indicates valid data is again available at fifo a output stage, si b is held high, awaiting bubble-up of empty location. 6. dir a goes high; (bubble-up delay after so a low) an empty location is present at input stage of fifo a .
1998 jan 23 19 philips semiconductors product speci?cation 4-bit x 16-word fifo register 74hc/hct40105 fig.22 waveforms showing the functionally and inter- communication between two fifos (refer to fig.19). note to fig.22 sequence 1 (both fifos empty, starting shift-in process): after a mr pulse has been applied fifo a and fifo b are empty. the dor flags of fifo a and fifo b go low due to no valid data being present at the outputs. the dir flags are set high due to the fifos being ready to accept data. so b is held high and two si a pulses are applied (1). these pulses allow two data words to ripple through to the output stage of fifo a and to the input stage of fifo b (2). when data arrives at the output of fifo b , a dor b pulse is generated (3). when so b goes low, the first bit is shifted out and a second bit ripples through to the output after which dor b goes high (4). sequence 2 (fifo b runs full): after the mr pulse, a series of 16 si pulses are applied. when 16 words are shifted in, dir b remains low due to fifo b being full (5). dor a goes low due to fifo a being empty. sequence 3 (fifo a runs full): when 17 words are shifted in, dor a remains high due to valid data remaining at the output of fifo a .q na remains high, being the polarity of the 17th data word (6). after the 32th si pulse, dir remains low and both fifos are full (7). additional pulses have no effect. sequence 4 (both fifos full, starting shift-out process): si a is held high and two so b pulses are applied (8). these pulses shift out two words and thus allow empty locations to bubble-up to the input stage of fifo b , and proceed to fifo a (9). when the first empty location arrives at the input of fifo a , a dir a pulse is generated (10) and a new word is shifted into fifo a .si a is made low and now the second empty location reaches the input stage of fifo a , after which dir a remains high (11). sequence 5 (fifo a runs empty): at the start of sequence 5 fifo a contains 15 valid words due to two words being shifted out and one word being shifted in sequence 4. an additional series of so b pulses are applied. after 15 so b pulses, all words from fifo a are shifted into fifo b . dor a remains low (12). sequence 6 (fifo b runs empty): after the next so b pulse, dir b remains high due to the input stage of fifo b being empty (13). after another 15 so b pulses, dor b remains low due to both fifos being empty (14). additional so b pulses have no effect. the last word remains available at the output q n .
1998 jan 23 20 philips semiconductors product speci?cation 4-bit x 16-word fifo register 74hc/hct40105 package outlines unit a max. 1 2 b 1 cee m h l references outline version european projection issue date iec jedec eiaj mm inches dimensions (inch dimensions are derived from the original mm dimensions) sot38-1 92-10-02 95-01-19 a min. a max. b max. w m e e 1 1.40 1.14 0.055 0.045 0.53 0.38 0.32 0.23 21.8 21.4 0.86 0.84 6.48 6.20 0.26 0.24 3.9 3.4 0.15 0.13 0.254 2.54 7.62 0.30 8.25 7.80 0.32 0.31 9.5 8.3 0.37 0.33 2.2 0.087 4.7 0.51 3.7 0.15 0.021 0.015 0.013 0.009 0.01 0.10 0.020 0.19 050g09 mo-001ae m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 16 1 9 8 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. (1) (1) d (1) z dip16: plastic dual in-line package; 16 leads (300 mil); long body sot38-1
1998 jan 23 21 philips semiconductors product speci?cation 4-bit x 16-word fifo register 74hc/hct40105 x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 8 9 1 16 y pin 1 index unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 1.0 0.4 sot109-1 95-01-23 97-05-22 076e07s ms-012ac 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.39 0.38 0.16 0.15 0.050 1.05 0.041 0.244 0.228 0.028 0.020 0.028 0.012 0.01 0.25 0.01 0.004 0.039 0.016 0 2.5 5 mm scale so16: plastic small outline package; 16 leads; body width 3.9 mm sot109-1
1998 jan 23 22 philips semiconductors product speci?cation 4-bit x 16-word fifo register 74hc/hct40105 unit a 1 a 2 a 3 b p cd (1) e (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 1.25 7.9 7.6 1.03 0.63 0.9 0.7 1.00 0.55 8 0 o o 0.13 0.2 0.1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. sot338-1 94-01-14 95-02-04 (1) w m b p d h e e z e c v m a x a y 1 8 16 9 q a a 1 a 2 l p q detail x l (a ) 3 mo-150ac pin 1 index 0 2.5 5 mm scale ssop16: plastic shrink small outline package; 16 leads; body width 5.3 mm sot338-1 a max. 2.0
1998 jan 23 23 philips semiconductors product speci?cation 4-bit x 16-word fifo register 74hc/hct40105 unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.40 0.06 8 0 o o 0.13 0.1 0.2 1.0 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot403-1 mo-153 94-07-12 95-04-04 w m b p d z e 0.25 18 16 9 q a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 a max. 1.10 pin 1 index
1998 jan 23 24 philips semiconductors product speci?cation 4-bit x 16-word fifo register 74hc/hct40105 soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). dip s oldering by dipping or by wave the maximum permissible temperature of the solder is 260 c; solder at this temperature must not be in contact with the joint for more than 5 seconds. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (t stg max ). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. r epairing soldered joints apply a low voltage soldering iron (less than 24 v) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may be up to 5 seconds. so, ssop and tssop r eflow soldering reflow soldering techniques are suitable for all so, ssop and tssop packages. reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. w ave soldering wave soldering can be used for all so packages. wave soldering is not recommended for ssop and tssop packages, because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. if wave soldering is used - and cannot be avoided for ssop and tssop packages - the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end. even with these conditions: only consider wave soldering ssop packages that have a body width of 4.4 mm, that is ssop16 (sot369-1) or ssop20 (sot266-1). do not consider wave soldering tssop packages with 48 leads or more, that is tssop48 (sot362-1) and tssop56 (sot364-1). during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. r epairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1998 jan 23 25 philips semiconductors product speci?cation 4-bit x 16-word fifo register 74hc/hct40105 definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.

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